module fun_decoder(
	input	clkIn,
	input	rst_n,

	input	[111:0]	aw,
	input	[111:0]	ar,

	inout	[31:0]	PXI_LD
);

wire[31:0] test;
r_mod UTeRd(//r(0,test)
	.aw_r_in(ar[0]),
	.clkin(clkIn),
	.busdata(PXI_LD),
	.rstin(test)
);
w_r_mod UTeWr(//w(0,test)
	.aw_r_in(aw[0]),
	.clkin(clkIn),
	.busdata(PXI_LD),
   .rstout(test)
);

endmodule
